1. Field of the Invention
The invention relates to a direct data transfer, by an address mapping scheme, between a plurality of devices connected to a bus.
A direct data transfer between a plurality of devices in a system having a processor is generally not possible, because a data is first sent from a device to a main memory unit by a DMA (Direct Memory Access) controller, then this data is sent from the main memory unit to an another device by a DMA controller of the other device. For this reason, the data transfer between devices is time consuming. In addition, a high load on the main memory upon data transfer slow the rate of the data transfer between a central processing unit and the main memory unit.
To shorten the time and to reduce the load on the main memory unit, there is a method to perform the direct data transfer between devices under a control of input/output (I/O) processors such as I/O controllers, without involving the main memory unit. Such data transfer is performed under the control of an I/O processor using its special monitor program. Normally, for input/output operations, a structure of file and a buffering control of main memory unit are under control of the operating system, rather than the I/O processor. That is, the I/O processor can perform the input/output operations using a physical block number converted by the operating system. The I/O processor cannot perform the I/O operations using a logical unit of data called a file or a record.
The reasons for not being able to perform I/O at the logical unit of data (file or record) follows. In general, the structure of file and the buffering control of main memory will be different for different operating systems and file systems, therefore, if the I/O processor is designed to have a function that relies on a certain file structure and a certain buffering operation, since the I/O processor is reliant on the specific operating system and the file system, when modifying or exchanging the operating system and the file system, the I/O processor must also be modified or exchanged. In addition, function allotments for the operating system and the I/O processor must be changed extensively.
2. Description of the Related Art
FIG. 9 is a schematic view of conventional configuration for direct data transfer between devices. FIG. 10 illustrates states of a virtual address space and a physical address space. A description of numbered components indicated in FIG. 9: is as follows a central processing unit 1 (CPU); a main memory unit 2; magnetic disk drives 4 and 4a; disk controllers 5 and 5a; and memories 80 and 80a. Following is the description of numbered components indicated in FIG. 10: a physical address space 23; a virtual address space 20; a user space 21; a user program 22; a buffer 39; device memories 26 and 26a; device memories 25 and 25a; and an address translation table 24. The physical address space is a range of addresses that the CPU can physically and directly access. For example, the physical address space of a CPU which can specify addresses having 32 bits is 2.sup.32 .apprxeq.4G. The user space 21 is an area where the user program 22 can make a direct access in the virtual address space 20. The buffer 32 is an area used by the user program 22 for data input/output. The common area 33 in the virtual address space 20 is a memory area which is used by the operating system. The remaining virtual address space not used by the operating system is assigned to the user spaces. Each user space is assigned to different parts of virtual address space. The device memories 25 and 25a assigned to the physical address space 23 are mapped to device memories 26 and 26a of the common area 33. The device memories 25 and 25a are the memories 80 and 80a inside the disk controllers 5 and 5a. The memories 80 and 80a can be directly accessed by the operating system. These memories receives read and write commands to the magnetic disk controller from the operating system. The operating system performs address translation from the device memories 26 and 26a which is mapped to the virtual address space 20 to the device memories 25 and 25a according to the address translation table 24 in the physical address space 23.
An advantage of assigning the memory area used by the operating system to the common area 33 is that a common process can be executed when a control moves from a user program to the operating system by a system call or an interrupt from any of the address space. Also, by assigning the device memories 25 to the common area 33, it becomes possible for the operating system to operate a device. For example, when the operating system writes a read command to the device memory 25 for a file, the disk controller 5 executes the read command and transfers the file stored at the magnetic disk drive 4 to the buffer 31 of the main memory unit 2. Likewise, when the operating system writes a write command to the device memory 25a for the file, the disk controller 5 executes the write command and transfers the file to the magnetic disk drive 4a from the buffer 31 of the main memory unit 2. Thus, a data transfer in file unit becomes possible by the operating system.
The conventional configuration of direct data transfer between devices and the states of virtual address space 20 and physical address 23 are described accordingly. Since the I/O processor does not know the file structure or the buffering operation, I/O control at a logical unit, such as a file is not possible for the I/O processor. On the other hand, for an interface level of system call of the operating system, a source address of transfer or a destination address of transfer for file input/output has to be the main memory unit 2 which is mapped to the user space 21. An address of source or destination of transfer must be specified using the virtual address. However, the virtual address corresponding to device memory 25 is not present at the user space 21 where the user program 22 can direct access, therefore, the input/output operations of file (where device memory is source of transfer or destination of transfer) is not possible for the user program 22. The virtual address corresponding to device memory 25 is present at common area 33. The common area 33 is an area used by the operating system so the user program 22 can not make a direct access to the common area 33.
A problem with the conventional data transfer apparatus between devices and its method is, when the I/O processor is being used, direct data transfer is only possible in physical block units, and data transfer is not possible in logical file units or logical record units.